1. Field of the Invention
The present invention relates to a method for supporting and verifying the design of a large-scale integrated circuit (LSI) and a program for executing the method in a computer. In particular, the present invention relates to a top-down design technique employing logic synthesis to automatically change a register transfer level (RTL) description of a hierarchical circuit into one that allows easy design verification.
2. Description of the Related Art
Recent large-scale semiconductor circuits involve a large amount of design data that is difficult to collectively handle in the verification, logic synthesis, and layout stages. To cope with this problem, the design data of a large-scale circuit is usually divided into layers or modules.
There are, however, no established design support methods or programs to effectively divide design data into layers or modules. Accordingly, circuit design projects frequently employ different design support methods or programs, which deteriorate design efficiency.